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Home > Thèses et HDR > Thèses en 2011

Matthieu DELOGE - 15/12/2011 - INSA

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Matthieu DELOGE soutient sa thèse le 15 décembre 2011 - Bât. Sadi Carnot INSA

Titre :

Analysis of ultrathin gate-oxide breakdown mechanisms and applications to antifuse memories fabricated in advanced CMOS processes.

Jury :

  • Directeur de thèse : Bruno ALLARD
  • Rapporteurs : Paolo PAVAN ; Gérard GHIBAUDO
  • Examinateurs : Philippe CANDELIER ; Joël DAMIENS ; Jean-Michel PORTAL

Résumé :

Non-volatile one-time programmable memories are gaining an ever growing interest in embedded electronics. Chip ID, chip configuration or system repairing are among the numerous applications addressed by this type of semiconductor memories. In addition, the antifuse technology enables the storage of secured information with respect to cryptography or else.
The thesis focuses on the understanding of ultrathin gate-oxide breakdown physics that is involved in the programming of antifuse bitcells. The integration of advanced programming and detection schemes is also tackled in this thesis. The breakdown mechanisms in the dielectric material SiO2 and high-K under a high electric field were studied. Dedicated experimental setups were needed in order to perform the characterization of antifuse bitcells under the conditions define in memory products. Typical time-to-breakdown values shorter than a micro second were identified. The latter measurements allowed the statistical study of dielectric breakdown and the modeling in a high voltage range, i.e. beyond the conventional range studied in reliability. The model presented in this PhD thesis enables the optimization of the antifuse bitcell sizes according to a targeted mean time-to-breakdown value. A particular mechanism leading to a high bulk current overshoot occurring during the programming operation was highlighted. The study of this phenomenon was achieved using electrical characterizations and simulations. The triggering of a parasitic P-N-P bipolar transistor localized in the antifuse bitcell appeared as a relevant hypothesis.
The analysis of the impact of the programming conditions on the resulting read current measured under a low voltage was performed using analog test structures. The amplitude of the programming current was controlled in an augmented antifuse bitcell. The programming time is controlled by a programming detection system and a delay.
Finally, these solutions are to be validated using a 1-kb demonstrator yet designed and fabricated in a logic 32-nm CMOS process.

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