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Home > Thèses et HDR > Thèses en 2020

19/11/2020 - Mamadou Lamine BEYE

by Laurent Krähenbühl - published on , updated on

Agenda

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Mamadou Lamine Beye defends his PhD on Nov. 19, 2020 at 1:30 PM.
Place : visio conference only. [930 6254 5226],

Contribution to the development of gate driver for GaN transistors

Jury :
M ALLARD Bruno : Professeur des Universités Professeur à l’INSA de Lyon (Ampere), Directeur de thèse
M MAHER Hassan : Professeur des Universités (3IT- LN2), Co directeur de thèse
MME ALONSO Corinne : Professeur des Universités LAAS CNRS, Rapporteur
M TROVAO Joao : Professeur à l’université de Sherbrooke, Examinateur
M COUSINEAU Marc : Maître de Conférences à l’INP Toulouse, Rapporteur
M IDIR Nadir : Professeur des Universités à l’Université de Lille, Président
MME BERKANI Mounira : Maître de Conférences Université Paris-Est Créteil, Examinatrice
M Luong Viêt Phung : Maitre de conférences, Ampère, INSA LYON : Co-encadrant
M Jean-François MOGNIOTTE : Enseignant-chercheur : Co-encadrant

Abstract :
This thesis is part of the sustainable development context where the energy challenges rely on designing numerous and lumped power converters with good power density and high efficiency. New power semiconductor devices, namely wide band semiconductors (GaN, SiC) are used in designing the converters. The high frequency control of these converters makes the system more sensitive to parasitic elements. The latter elements disrupt the switching behavior of the transistors and generate additional losses. In this context this work was carried out in a cotutelle partnership between Ampère Laboratory in Villeurbanne and LN2 laboratory at the University of Sherbrooke; the aim being to make a contribution in optimizing the switching conditions of GaN HEMTs.

The first work axis consists in managing the voltage and current switching speed through gate control strategies in order to improve the conducted EMI. Firstly, most of the proposed control circuits are developed in open-loop and then secondly in closed-loop in order to compensate the effects of non-linearities (with respect to temperature, load current and operating voltage). Concerning the development of control systems, it can be done first by the use of available discrete components, then by the alternative of the monolithic GaN integration which is considered in order to bring more speed and efficiency. Monolithic integration would also solve the problem of parasitic inductances. To facilitate the design of integrated circuits and control systems, the development of a behavioral model of HEMT GaN will serve as a modeling tool.

The second axis of the work consists in experimentally validating well-adapted control system for the gate of the power transistor in order to master the transient behaviors of the power transistors. Namely it is necessary to allow a satisfying management of losses during dead time in a half bridge converter.

At the end of this work, the control systems developed in open loop made it possible to slow the switching speeds by at least 30 % but causing an increase in switching losses up to 50% in some cases. Due to the fast switching speed of HEMT GaNs and the limitations of discrete components on the market, the reduction rate of switching speeds obtained with the closed loop (reduction rate less than 20%) is less attractive than that of the open loop. Using a monolithic circuit can be an alternative to increase the rate of reduction of closed loop switching speeds. SPICE simulation toward monolithic circuit are the basis of this hypothesis. Concerning the second axis, the application of multilevel gate voltage control of the transistors of half bridge made it possible to reduce the losses of reverse conduction and the losses due to the phenomena of Cross Talk by at least by 30 %.

Key Words : HEMT GaN; gate driver; adaptative control; transistor modeling


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