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Home > Thèses et HDR > Thèses en 2019

10/04/2019 - Eric FELTRIN

by Laurent Krähenbühl - published on , updated on


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Eric Feltrin soutient sa thèse le 10/04/2019 à 10:00.
Lieu : amphi 202, Bâtiment W1), Ecole Centrale de Lyon (Ecully).

Analysis of noise of a buck converter on analog IPs integrated in a SoC and development of minimization techniques

Jury :
Rapporteurs : Marie-Minerve Louerat - Aleksandar Prodic
Examinateurs : Françoise Paladian - Etienne Sicard
Encadrement : Christian Vollaire, Bruno Allard
Invité : Jose Cobos

Abstract :
The micro-controller market is undergoing changes and is expected to grow quickly promoted by the Internet-of-Things (IoT) development. Calculation capability, connectivity, analog performances and power efficiency are key enablers.
Power management unit is co-integrated with the micro-controller so that only few off-chip passive components are necessary. The embedded power management unit must deliver the micro-controller input voltage along with the power demand which increases with the computation capability. The chosen architecture has to optimize the efficiency in high and low power mode but without impacting analog performance of sensitive IPs.
The active part of an inductive buck converter is integrated but some switching noise is observed that severely impact analog IPs.
The objective of this work is the analysis the noise generation from the power stage and its propagation in the SoC.
The generation model is constituted of a RLC equivalent circuits in each state of the power stage. The R, L and C expressions are detailed depending on physical parasitic components. These models permit to understand noise mechanisms and to give an estimation of the noise amplitude and frequency resonance. The models show the degrees of freedom to manage the noise signature.
The whole system, i.e. the electronic board, the package and the chip, is modeled to extract the system-level propagation path between the buck converter and sensitive IPs.
These models are verified by measurement on a test vehicle.
Finally three solutions are presented to reduce the buck converter noise impact: two changes in the power stage architecture to reduce noise generation and one modification of the top routing of the power delivery network to improve isolation between parts of the circuit regarding noise susceptibility.
The thesis contributes an original methodology to build the missing models at system-level regarding noise generation and propagation from the switching power supply. Knowledge has been acquired, experimentally verified and supported by the design of a demonstrator (to be tested).

Key Words : switching noise – buck converter – noise propagation – noise modeling – micro-controller – System-on-Chip